The present invention relates generally to semiconductor memory devices and more particularly to a semiconductor memory device having a serial access mode that includes a latency period and a serial access period.
In order to improve operation speeds, semiconductor memory devices can have a serial access mode of operation. In a serial access mode of operation, a read command is received by the semiconductor memory. Then, after a latency period, data is read out in a serial fashion.
A serial access mask ROM (read only memory) has a serial access mode of operation. When a serial access mask ROM receives a read command, a word line is activated based on a received address. The time required to activate the word line and access the first bits of data is defined as the latency period. The time to access subsequent bits of data in a sequential fashion can be called a serial access period. The data can be serially accessed synchronously with an external read clock signal that is applied to the semiconductor memory device.
In a semiconductor memory device having such a serial access mode, the data transfer speed can be improved by shortening the latency period. The latency period can be shortened by providing a faster access to the first bits of data. The data transfer speed can also be improved by shortening the access times during the serial access period.
Another factor in the design of a semiconductor memory device is chip size. In order to reduce chip size, the word line length is made as long as possible, which reduces the number of row decoders needed. Because bits are typically accessed serially from the same word line, lengthening the word line can also allow more bits to be serially accessed in one serial access mode operation. However, this can effect the latency period because a longer word line is slower to rise due to the larger resistive and capacitive load.
Memory cells in a serial access mask ROM can be programmed in one of two different states. The programmed state indicates whether the data value stored in the memory cell is logic one or logic zero. The states of the memory cell can be termed as an ON-cell or an OFF-cell. An on-cell is a memory cell that has been programmed to be conductive when selected by a word line. An OFF-cell is a memory cell that has been programmed to be non-conductive when selected by a word line. Each memory cell is typically an n-channel insulated gate field effect transistor (IGFET), which can be programmed to be an OFF-cell by programming a high threshold voltage or to be an ON-cell by programming a low threshold voltage. This can be done with an ion implantation step, as just one example. In this example, it is assumed that the memory cell is a NAND type cell.
An example of a conventional serial access mask ROM will now be described with reference to a sense amplifier set forth in FIG. 3 and a timing diagram set forth in FIG. 5. The conventional serial access mask ROM has a serial mode of operation in which there is a latency period and serial access period.
Referring now to FIG. 3, a sense amplifier is set forth in a circuit schematic diagram and given the general reference 110. The sense amplifier detects whether a selected memory cell is an ON-cell or an OFF-cell by comparing a sense level at a sense node N306 with a reference voltage REF. This is done by having sense node N306 and reference voltage REF as inputs to differential amplifier 304. Differential amplifier 304 provides a data output SOUT based on the comparison. In the conventional serial mask ROM, the reference voltage is at a midpoint of the voltage swing of the sense node N306.
Differential amplifier 304 can be electrically connected to a selected memory cell by a column selector and memory cell digit lines 307 by way of a input node N305. When a memory cell is selected, the state of the memory cell (ON-bit or OFF-bit) determines the potential of sense node N306.
Referring now to FIG. 5, waveforms indicating a serial access mode operation of a conventional serial access ROM are set forth. The waveforms pertaining to a serial access mode operation of a conventional serial access ROM are labeled as xe2x80x9cBACKGROUND ART.xe2x80x9d
FIG. 5 represents a serial access mode read operation and illustrates the latency period and serial access period.
At time t2, conventional serial access ROM enters the latency period in which a word line is selected based on the address that has been applied. It is noted that in the conventional serial access ROM, digit lines adjacent to the digit line associated with the selected cell are discharged to ground in order to prevent excessively charging of digit lines.
Thus, at time t2, based on the received row address, a word line is selected. At the same time, a digit line is selected based on a received column address. Thus, the selected word line can begin to rise. The potential of the selected digit line can begin to rise also. This is due to the p-channel load IGFET 301 in the sense amplifier 110 illustrated in FIG. 3. However, due to the word line having a larger capacitive and/or resistive load, the selected word line rises at a slower rate than the selected digit line.
Assuming that the first bit read during the latency period is an ON-cell, once the word line achieves a high enough voltage to turn on the n-channel IGFET memory cell, the selected digit line begins to discharge. It is noted that because the digit-line charges up during the precharge period before the word line rises to a sufficient level to turn on the ON-bit selected memory cell, the sense node N306 can achieve a relatively high precharge voltage.
After the word line reaches a high enough voltage for the selected ON-cell to conduct, the digit line can be discharged toward a ground level. This can be seen as dashed line of SENSE LEVEL signal (corresponding to sense node N306) in the BACKGROUND art waveforms of FIG. 5. When the sense node N306 reaches a level below the voltage reference REF, the sense amplifier 110 can correctly produce a sense amp output SOUT at a logic level (high in this case) corresponding to an ON-bit cell.
Next, at time t3, a clock RCLOCK makes a transition, which is the beginning of the serial access portion of the serial access mode. A column address is incremented and a different digit line is selected. During this read cycle, the memory cell associated with the selected digit line and already selected word line is an off-bit cell. The OFF-bit cell does not conduct current and the digit line can be pulled up by the p-channel load transistor 301. Once the SENSE LEVEL signal (sense node N306) reaches a voltage level above the voltage reference REF, the sense amplifier 110 can correctly produce a sense amp output SOUT at a logic level (low in this case) corresponding to an OFF-bit cell.
It is noted that the drive strength of p-channel load transistor 301 decreases as the digit line rises. This is because the gate to source voltage is decreased. Thus, although the digit line may rise relatively fast at first, the drive strength can decrease as the digit line potential gets closer to the reference voltage VREF. Thus, the reading of the OFF-bit cell can be slow.
Illustrated in the read cycle between times t3 and t4, is a dashed waveform which can correspond to an ON-bit cell being read. It can be seen from the sense amp output SOUT, that an ON-bit cell can be read faster than an OFF-bit cell in the serial access portion of a serial access mode. However, compared to the latency portion, it can be seen from the sense amp output SOUT, that an OFF-bit cell is read faster than an ON-bit cell in the serial access portion of a serial access mode.
The access time of a semiconductor memory device is determined by the slowest bit read. Thus, the access time is limited when one type of bit is read more slowly under certain conditions.
In view of the above discussion, it would be desirable to provide a semiconductor device having a serial access mode of operation in which access times may be improved during the latency portion. It would also be desirable to provide improved access times during a serial access portion.
According to the present embodiments, a semiconductor memory device having serial access read mode including a latency period and serial access period is provided. The semiconductor memory device can include a sense amplifier receiving a reference voltage having a first potential during the latency period and a second potential during the serial access period.
According to one aspect of the embodiments, the reference voltage can have a higher potential in the latency period than in the serial access period.
According to another aspect of the embodiments, the semiconductor memory device can include a reference voltage generator. The reference voltage generator can receive a control signal and may provide a reference voltage having a potential determined by the logic level of the control signal.
According to another aspect of the embodiments, the reference voltage generator can include a load circuit coupled between a supply voltage and a reference voltage. The load circuit can have a first impedance when a control signal is at a first logic level and a second impedance when the control signal is at a second logic level. The first impedance can be less than the second impedance.
According to another aspect of the embodiments, the reference voltage generator can include a load circuit providing the reference potential according to a load current. The reference voltage generator can also include a selection circuit for providing a first load current when the control signal is at the first logic level and a second load current when the control signal is at a second logic level.
According to another aspect of the embodiments, the first load current can be determined by the impedance of a first dummy memory cell. The second load current can be determined by the impedance of a second dummy memory cell.
According to another aspect of the embodiments, the semiconductor memory device can be a read only memory.
According to another aspect of the embodiments, the semiconductor memory device can have a read operation including a first bit access and a subsequent bit access and the sense amplifier can receive a different reference voltage on the first bit access than on the subsequent bit access.
According to another aspect of the embodiments, the sense amplifier can receive a data signal. The data signal may have a data signal switching range based on opposite states of a memory cell. The reference voltage potential can be higher than the mid-point of the data signal switching range during the latency period.
According to another aspect of the embodiments, the reference potential can be lower than the mid-point of the data signal switching range during the serial access period.
According to another aspect of the embodiments, the semiconductor memory device can include a control circuit generating a control signal having a logic level determined by whether the semiconductor memory device is in the latency period or the serial access period.
According to another aspect of the embodiments, the control circuit can detect the latency period by detecting an external address load operation.
According to another aspect of the embodiments, the control circuit can include a latch circuit for latching a logic level when an external clock transitions, signaling the end of the latency period.
According to another aspect of the embodiments, the control circuit can receive an address set signal and a read clock signal and may produce a control signal indicating whether a serial access read operation is in the latency period or serial access period.